74AC373B datasheet(1/11 Pages) STMICROELECTRONICS

Il numero della parte	74AC373B

Spiegazioni elettronici	OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

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Produttore elettronici	STMICROELECTRONICS [STMicroelectronics]

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April 2001

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HIGH SPEED: tPD = 5ns (TYP.) at VCC = 5V

s

LOW POWER DISSIPATION:

ICC = 4µA(MAX.) at TA=25°C

s

HIGH NOISE IMMUNITY:

VNIH = VNIL = 28 % VCC (MIN.)

s

50

Ω TRANSMISSION LINE DRIVING

CAPABILITY

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SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 24mA (MIN)

s

BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

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OPERATING VOLTAGE RANGE:

VCC (OPR) = 2V to 6V

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PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 373

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IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74AC373 is a high-speed CMOS OCTAL

D-TYPE LATCH with 3 STATE OUTPUT NON

INVERTING fabricated with sub-micron silicon

gate and double-layer metal wiring C2MOS

technology.

These 8 bit D-Type latch are controlled by a latch

enable input (LE) and an output enable input (OE).

While the LE inputs is held at a high level, the Q

outputs will follow the data input. When the LE is

taken low, the Q outputs will be latched at the

logic level of D input data. While the (OE) input is

low, the 8 outputs will be in a normal logic state

(high or low logic level); while OE is in high level

the outputs will be in a high impedance state.

This device is designed to interface directly High

Speed CMOS systems with TTL and NMOS

components.

All

inputs

and

outputs

are

equipped

with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

74AC373

OCTAL D-TYPE LATCH

WITH 3 STATE OUTPUTS (NON INVERTED)

PIN CONNECTION AND IEC LOGIC SYMBOLS

ORDER CODES

PACKAGE

TUBE

T & R

DIP

74AC373B

SOP

74AC373M

74AC373MTR

TSSOP

74AC373TTR

TSSOP

DIP

SOP

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74AC373B Scheda tecnica(PDF) 1 Page - STMicroelectronics

74AC373B Scheda tecnica(HTML) 1 Page - STMicroelectronics

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