RESET

POWER-DOWN MODE

LAYOUT OF PCB WITH PowerPAD

CONNECTING HIGH-SPEED,

ADS5273

SBAS305D – JANUARY 2004 – REVISED JANUARY 2009 .............................................................................................................................................. www.ti.com

It is recommended that the isolation be maintained

onboard by using separate supplies to drive AVDD

After the supplies have stabilized, it is required to

and LVDD, as well as separate ground planes for

give the device an active RESET pulse. This results

AVSS and LVSS.

in all internal registers getting reset to their default

The use of LVDS buffers reduces the injected noise

value of 0 (inactive). Without a reset, it is possible

considerably,

compared

to

CMOS

buffers.

The

that some registers might be in their non-default state

current in the LVDS buffer is independent of the

on power-up. This could cause the device to

direction of switching. Also, the low output swing, as

malfunction. When a reset is active, the device

well as the differential nature of the LVDS buffer,

outputs 0 code on all channels. However, the LVDS

results in low-noise coupling.

output clocks are unaffected by reset.

THERMALLY-ENHANCED PACKAGES

The ADS5273 has a power-down pin, referred to as

PD. Pulling PD high causes the device to enter the

The ADS5273 is housed in an 80-lead PowerPAD

power-down mode. In this mode, the reference and

thermally-enhanced package. To make optimum use

clock circuitry, as well as all the channels, are

of

the

thermal

efficiencies

designed

into

the

powered down. Device power consumption drops to

PowerPAD package, the printed circuit board (PCB)

less than 100mW in this mode. In power-down mode,

must be designed with this technology in mind.

the internal buffers driving REFT and REFB are

Please

refer

to

PowerPAD

brief

SLMA004,

tri-stated and their outputs are forced to a voltage

PowerPAD Made Easy (available for download at

roughly equal to half of the voltage on AVDD. Speed

www.ti.com),

which

addresses

the

specific

of recovery from power-down mode depends on the

considerations

required

when

integrating

a

value of the external capacitance on the REFT and

PowerPAD package into a PCB design. For more

REFB pins. For capacitances on REFT and REFB less

detailed information, including thermal modeling and

than 1

µF, the reference voltages settle to within 1%

repair

procedures,

please

see

technical

brief

of their steady-state values in less than 500

µs.

SLMA002, PowerPAD Thermally-Enhanced Package

Individual channels can also be selectively powered

(www.ti.com).

down by programming registers.

Interfacing High-Speed LVDS Outputs (SBOA104),

The ADS5273 also has an internal circuit that

an application report discussing the design of a

monitors the state of stopped clocks. If ADCLK is

simple deserializer that can deserialize LVDS outputs

stopped (or if it runs at a speed less than 3MHz), this

up to 840Mbps, can be found on the TI web site

monitoring circuit generates a logic signal that puts

(www.ti.com).

the device in a power-down state. As a result, the

power consumption of the device is reduced to less

than 100mW when ADCLK is stopped. The recovery

MULTI-CHANNEL ADCs TO XILINX FPGAs

from such a power-down could take approximately

A separate application report (XAPP774) describing

100

µs; this is described in Table 2.

how to connect TI's high-speed, multi-channel ADCs

with serial LVDS outputs to Xilinx FPGAs can be

downloaded

directly

from

the

Xilinx

web

site

(http://www.xilinx.com).

Table 2. Time Constraints Associated with Device Recovery from Power-Down and Clock Stoppage

DESCRIPTION

TYP

REMARKS

Recovery from power-down mode (PD = 1 to PD = 0).

500

µs

Capacitors on REFT and REFB less than 1µF.

Recovery from momentary clock stoppage ( < 300ns).

10

µs

Recovery from extended clock stoppage ( > 300ns).

100

µs

24

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