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LP3470A Scheda tecnica(PDF) 11 Page - Texas Instruments |
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LP3470A Scheda tecnica(HTML) 11 Page - Texas Instruments |
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11 / 23 page ![]() Overdrive Pulse Duration VCC V IT- V IT+ V HYS 11 LP3470A www.ti.com SNVSBF5C – JULY 2019 – REVISED MAY 2020 Product Folder Links: LP3470A Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Feature Description (continued) Figure 10. Overdrive vs Pulse Duration 8.4 Device Functional Modes 8.4.1 RESET Output Low When the VCC supply voltage is below the reset threshold (VIT-), the RESET pin will output logic low. RESET is ensured to be a logic low for VCC > 0.95 V. 8.4.2 RESET Output High When the VCC supply voltage exceeds the reset threshold (VIT-) plus the hysteresis voltage (VHYS), the RESET remains asserted for a time period (tD) programmed by an external capacitor (CSRT); after this interval RESET goes to logic high. |
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