1

2

3

6

5

4

BATT

GND

IN

EN

NC

OUT

CIN

CBATT

COUT

CIN

CBATT

OUT

IN

GND

A3

A1

BATT

B2

C3

C1

OUT2

EN

COUT

LP5952

SNVS469F – OCTOBER 2006 – REVISED DECEMBER 2015

www.ti.com

10 Layout

10.1 Layout Guidelines

For best overall performance, place all circuit components on the same side of the circuit board and as near to

the respective LDO pin connections as practical. Place ground return connections as close as possible to the

input and output capacitor and to the LDO ground pin, connected by a wide, copper surface. The use of vias and

long traces to create LDO circuit connection is strongly discouraged and negatively affect system performance.

10.2 Layout Examples

Figure 19. LP5952 DSBGA Layout Example

Figure 20. LP5952 WSON Layout Example

18

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