PUSB3FR6

All information provided in this document is subject to legal disclaimers.

© NXP Semiconductors N.V. 2015. All rights reserved.

Product data sheet

Rev. 1 — 25 February 2015

7 of 12

NXP Semiconductors

PUSB3FR6

ESD protection for ultra high-speed interfaces

7.

Package outline

IEC 61000-4-5; tp =8/20 s; positive pulse

IEC 61000-4-5; tp =8/20 s; negative pulse

Fig 10. Dynamic resistance with positive clamping;

typical values

Fig 11. Dynamic resistance with negative clamping;

typical values

VCL (V)

08

6

24

aaa-016890

4

2

6

8

IPP

(A)

0

VCL (V)

-8

0

-2

-6

-4

aaa-016891

-4

-6

-2

0

IPP

(A)

-8

Fig 12. Package outline DFN2111-7 (SOT1358-1)

14-05-07

Dimensions in mm

0.1

0.25

0.15

0.5

0.3

0.5

1.5

1.0

2.20

2.05

0.5

max

0.2

min

0.05 max

0.127

1.2

1.0

1

4

5

7