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PCM1804DBR Scheda tecnica(PDF) 24 Page - Texas Instruments

Il numero della parte PCM1804DBR
Spiegazioni elettronici  FULL DIFFERENTIAL ANALOG INPUT 24-BIT, 192-kHz STEREO A/D CONVERTER
PDF  39 Pages
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Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
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PCM1804DBR Scheda tecnica(HTML) 24 Page - Texas Instruments

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BCK
LRCK
DATA
tw(BCKH)
tw(BCKL)
t(LRHD)
t(LRCP)
t(LRSU)
t(BCKP)
t(CKDO)
t(LRDO)
1.4 V
1.4 V
0.5 VDD
T0017-03
INTERFACE TIMING FOR DSD
Dn−3
Dn−2
Dn−1
Dn
Dn+1
Dn+2
Dn+3
Dn−3
Dn−2
Dn−1
Dn
Dn+1
Dn+2
Dn+3
DSDBCK
DSDL
DSDR
T0052−01
PCM1804
SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
PARAMETERS
MIN
TYP
MAX
UNIT
t(BCKP)
BCK period
1/(64 fS)
1/(48 fS)
tw(BCKH)
BCK pulse duration, HIGH
32
ns
tw(BCKL)
BCK pulse duration, LOW
32
ns
t(LRSU)
LRCK setup time to BCK rising edge
12
ns
t(LRHD)
LRCK hold time to BCK rising edge
12
ns
t(LRCP)
LRCK period
1/fS
t(CKDO)
Delay time, BCK falling edge to DATA valid
5
25
ns
t(LRDO)
Delay time, LRCK edge to DATA valid
5
25
ns
tr
Rising time of all signals(1)(2)
10
ns
tf
Falling time of all signals(1)(2)
10
ns
(1)
Rising and falling times are measured from 10% to 90% of IN/OUT signals swing.
(2)
Load capacitance of DATA/DSDR signal is 10 pF.
Figure 38. Audio Data Interface Timing for PCM (Slave Mode: LRCK and BCK Work as Inputs)
Figure 39 and Figure 40 illustrate the interface timing for DSD.
Figure 39. Audio Data Format
24
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Copyright © 2001–2007, Texas Instruments Incorporated
Product Folder Link(s): PCM1804



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