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STM32F207VCY6TR Scheda tecnica(PDF) 109 Page - STMicroelectronics |
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STM32F207VCY6TR Scheda tecnica(HTML) 109 Page - STMicroelectronics |
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109 / 184 page ![]() DocID15818 Rev 15 109/184 STM32F20xxx Electrical characteristics 183 01 fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD > 2.70 V - - 25 MHz CL = 50 pF, VDD > 1.8 V - - 12.5 CL = 10 pF, VDD > 2.70 V - - 50(3) CL = 10 pF, VDD > 1.8 V - - 20 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time CL = 50 pF, VDD >2.7 V - - 10 ns CL = 50 pF, VDD > 1.8 V - - 20 CL = 10 pF, VDD > 2.70 V - - 6 CL = 10 pF, VDD > 1.8 V - - 10 10 fmax(IO)out Maximum frequency(2) CL = 40 pF, VDD > 2.70 V - - 25 MHz CL = 40 pF, VDD > 1.8 V - - 20 CL = 10 pF, VDD > 2.70 V - - 100(3) CL = 10 pF, VDD > 1.8 V - - 50(3) tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time CL = 40 pF, VDD > 2.70 V - - 6 ns CL = 40 pF, VDD > 1.8 V - - 10 CL = 10 pF, VDD > 2.70 V - - 4 CL = 10 pF, VDD > 1.8 V - -3 6 11 fmax(IO)out Maximum frequency(2) CL = 30 pF, VDD > 2.70 V - - 100(3) MHz CL = 30 pF, VDD > 1.8 V - - 50(3) CL = 10 pF, VDD > 2.70 V - - 120(3) CL = 10 pF, VDD > 1.8 V - - 100(3) tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time CL = 30 pF, VDD > 2.70 V - - 4 ns CL = 30 pF, VDD > 1.8 V - - 6 CL = 10 pF, VDD > 2.70 V - - 2.5 CL = 10 pF, VDD > 1.8 V - - 4 -tEXTIpw Pulse width of external signals detected by the EXTI controller -10 - - ns 1. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F20/21xxx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 2. The maximum frequency is defined in Figure 39. 3. For maximum frequencies above 50 MHz and VDD above 2.4 V, the compensation cell should be used. Table 48. I/O AC characteristics(1) (continued) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions Min Typ Max Unit |
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