ICM7620/7610/7600

Rev. A7

ICmic reserves the right to change specifications without prior notice

7

LDAC

WR

A1

A0

LATCH STATE

1

1

X

X

Input and DAC data latched

1

0

0

0

Input Latch transparent – DAC A

0

1

X

X

DAC Latch transparent – All DACs

0

0

0

0

DAC latch of All DACs transparent and DAC A input latch transparent

1

0

0

1

Input Latch transparent – DAC B

1

0

1

0

Input Latch transparent – DAC C

1

0

1

1

Input Latch transparent – DAC D

Table 1. Address Table

DETAILED DESCRIPTION

The ICM7620 is a 12-bit voltage output Quad DAC. The ICM7610 is the 10-bit version of this family and the ICM7600 is the 8-bit

version. These devices have a parallel interface and each DAC has a double buffered input. This family of DACs has a

guaranteed monotonic behavior. The operating supply range is from 2.7V to 5.5V.

Reference Input

The reference input accepts positive DC and AC signals. The voltage at REFIN sets the full-scale output voltage of all the DACs.

The reference input voltage range is from 0 to VDD-1.5V. The impedance at this pin is nominally about 40 K . Each DACs output

the output voltage for any code, use the following equation.

ICM7620, 10 for ICM7610 and 8 for ICM7600.

Output Buffer Amplifier

The Quad DAC has 4 output amplifiers connected in a gain of 2 configuration. These amplifiers have a wide output voltage swing.

The actual swing of the output amplifiers will be limited by offset error and gain error. See the Applications Information Section for

a more detailed discussion.

The output amplifier can drive a load of 2.0 K

typical settling time of 8 s.

Input Logic

This quad DAC family uses a standard straight parallel interface where D0 is the LSB and D11 is the MSB for the ICM7620, D9 is

the MSB for the ICM7610 and D7 is the MSB for the ICM7600. Each DAC has its own double buffered input with an input latch

and a DAC latch. Each DAC will go the voltage output that corresponds to the digital data that is stored in its DAC latch.

The WR Input (active low), controls the input latch data and the LDAC Input (active low) updates the DAC latches (Table 1).

Please refer to the Timing Diagram for more detail. The address inputs (A1, A0) control DAC addressing (Table 1).

Power-Down Mode

These parts offer shutdown capability to the user by means of the SHDN pin. When this pin is forced high all the DACs power

down and the REF input goes into high impedance state. The total current consumption will go down to below 10 A in power

down mode. The data is stored in the latches during power down and the DACs will power up in the previous state when SHDN is

driven back to logic low.

Power-On Reset

There is a power-on reset on board that will clear the contents of all the latches to all 0s on power-up and the DAC voltage output

will go to ground.