PIC16F753 datasheet(9/230 Pages) MICROCHIP

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DS40001709C-page 9

PIC16F753/HV753

2.0

MEMORY ORGANIZATION

2.1

Program Memory Organization

The PIC16F753/HV753 has a 13-bit program counter

capable of addressing an 8K x 14 program memory

space. Only the first 2K x 14 (0000h-07FFh) is

physically implemented. Accessing a location above

these boundaries will cause a wrap-around within the

first 2K x 14 space for PIC16F753/HV753. The Reset

vector is at 0000h and the interrupt vector is at 0004h

(see Figure 2-1).

FIGURE 2-1:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F753/HV753

2.2

Data Memory Organization

The data memory (see Figure 2-2) is partitioned into four

banks, which contain the General Purpose Registers

(GPR) and the Special Function Registers (SFR). The

Special Function Registers are located in the first 32

locations of each bank. Register locations 40h-6Fh in

Bank 0 are General Purpose Registers, implemented as

static RAM. Register locations 70h-7Fh in Bank 0 are

Common RAM and shared as the last 16 addresses in

all Banks. All other RAM is unimplemented and returns

‘0’ when read. The RP<1:0> bits of the STATUS register

are the bank select bits.

RP1

RP0

 Bank 0 is selected

 Bank 1 is selected

 Bank 2 is selected

 Bank 3 is selected

2.2.1

GENERAL PURPOSE REGISTER

FILE

The register file is organized as 64 x 8 in the

PIC16F753/HV753. Each register is accessed, either

directly or indirectly, through the File Select Register

(FSR) (see Section 2.5 “Indirect Addressing, INDF

and FSR Registers”).

2.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (see Table 2-1). These

registers are static RAM.

The special registers can be classified into two sets:

core and peripheral. The Special Function Registers

associated with the “core” are described in this section.

Those related to the operation of the peripheral features

are described in the section of that peripheral feature.

PC<12:0>

0000h

0004h

0005h

07FFh

0400h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

Shadows 0-07FFh

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