TSC2014IYZGR datasheet(33/62 Pages) TI2

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I CWrite-AddressingByte

AD0

I CRead-AddressingByte

S/Sr

AD0

STARTor

RepeatedSTART

ACK

S/Sr

STARTor

RepeatedSTART

ACK

FromMastertoSlave

A=Acknowledge(SDALOW)

S=STARTCondition

Sr=RepeatedSTARTCondition

FromSlavetoMaster

TSC2014

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SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016

Product Folder Links: TSC2014

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7.5 Programming

7.5.1 Digital Interface

7.5.1.1 Address Byte

The TSC2014 has a 7-bit slave address word. The first six bits (MSBs) of the slave address are factory-preset to

comply with the I2C standard for A/D converters and are always set at '100100'. The logic state of the address

input pin determines the LSB of the device address to activate communication. Therefore, a maximum of two

devices with the same preset code can be connected on the same bus at one time.

The AD0 address input is only read during a power-up of the device, and should be connected to supply

(VDD/REF) or ground (GND). The slave address is latched into the TSC2014 on the falling edge of SCL after the

read/write bit has been received by the slave.

The last bit of the address byte (R/W) defines the operation to be performed. When set to a '1', a read operation

is selected; when set to a ‘0’, a write operation is selected. Following the START condition, the TSC2014

monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving the '10010' code, the

appropriate device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.

Table 5. I2C Slave Address Byte

MSB

LSB

AD0

R/W

7.5.1.1.1

Bit D0: R/W

1: I2C master read from TSC (I2C read addressing).

0: I2C master write to TSC (I2C write addressing).

Figure 32. I2C Bus Addressing (Slave Address Byte Format)

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