VIH

VIL

SMBCLK

P

S

VIH

VI

L

SMBDAT

tBUF

tHD;STA

tLOW

tR

tHD;DAT

tHIGH

tF

tSU;DAT

tSU;STA

tSU;STO

P

S

LM73

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SNIS141F – OCTOBER 2005 – REVISED OCTOBER 2015

6.7 Logic Electrical Characteristics- SMBus Digital Switching Characteristics

Unless otherwise noted, these specifications apply for VDD = 2.7 V to 5.5 V, CL (load capacitance) on output lines = 400 pF.

All limits TA = TJ = 25°C, unless otherwise noted. See Figure 1.

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX(2)

UNIT

No minimum clock

frequency if Time-

fSMB

SMBus Clock Frequency

TA = TJ =TMIN to TMAX

400

kHz

Out feature is

disabled.

tLOW

SMBus Clock Low Time

TA = TJ =TMIN to TMAX

300

ns

tHIGH

SMBus Clock High Time

TA = TJ =TMIN to TMAX

300

ns

tF;SMB

CL = 400 pF

Output Fall Time (3)

TA = TJ =TMIN to TMAX

250

ns

O

IPULL-UP ≤ 3 mA

SMBDAT and SMBCLK Time

tTIMEO

Low for Reset of Serial Interface

TA = TJ =TMIN to TMAX

15

45

ms

UT

(4)

Data In Setup Time to SMBCLK

tSU;DAT

TA = TJ =TMIN to TMAX

100

ns

High

tHD;DA Data Hold Time: Data In Stable

TA = TJ =TMIN to TMAX

0

ns

TI

after SMBCLK Low

tHD;DA Data Hold Time: Data Out Stable

TA = TJ =TMIN to TMAX

30

ns

TO

after SMBCLK Low

Start Condition SMBDAT Low to

SMBCLK Low (Start condition

tHD;STA

TA = TJ =TMIN to TMAX

60

ns

hold before the first clock falling

edge)

Stop Condition SMBCLK High to

tSU;ST

SMBDAT Low (Stop Condition

TA = TJ =TMIN to TMAX

50

ns

O

Setup)

SMBus Repeated Start-Condition

tSU;STA Setup Time, SMBCLK High to

TA = TJ =TMIN to TMAX

50

ns

SMBDAT Low

SMBus Free Time Between Stop

tBUF

TA = TJ =TMIN to TMAX

1.2

µs

and Start Conditions

tPOR

Power-On Reset Time (5)

TA = TJ =TMIN to TMAX

1

ms

(1)

Typicals are at TA = 25°C and represent most likely parametric norm.

(2)

Limits are specified to AOQL (Average Outgoing Quality Level).

(3)

The output fall time is measured from (VIH;MIN + 0.15V) to (VIL;MAX - 0.15V).

(4)

Holding the SMBDAT and/or SMBCLK lines Low for a time interval greater than tTIMEOUT will reset the LM73's SMBus state machine,

setting SMBDAT and SMBCLK pins to a high impedance state.

(5)

Represents the time from VDD reaching the power-on-reset level to the LM73 communications being functional. After an additional time

equal to one temperature conversion time, valid temperature is available in the Temperature Data Register .

Figure 1. SMBus Communication

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