500 LPFM

200 LFPM

No Air Flow

LM20146

www.ti.com

SNVS563C – FEBRUARY 2008 – REVISED APRIL 2013

To obtain an estimate of the device junction temperature, one may use the following relationship:

TJ = PDθJA + TA

(14)

and

PD = PIN x (1 - Efficiency) - 1.1 x IOUT2 x DCR

where

•

TJ is the junction temperature in °C

•

PIN is the input power in Watts (PIN = VIN x IIN)

•

θJA is the junction to ambient thermal resistance for the LM20146

•

TA is the ambient temperature in °C

•

IOUT is the output load current

•

DCR is the inductor series resistance

(15)

It is important to always keep the operating junction temperature (TJ) below 125°C for reliable operation. If the

junction temperature exceeds 160°C the device will cycle in and out of thermal shutdown. If thermal shutdown

occurs it is a sign of inadequate heatsinking or excessive power dissipation in the device.

Figure 36, shown below, provides a better approximation of the

θJA for a given PCB copper area on a 4 layer

board. The PCB heatsink area consists of 2oz. copper located on the bottom layer of the PCB directly under the

HTSSOP exposed pad. The bottom copper area is connected to the HTSSOP exposed pad by means of a 4 x 4

array of 12 mil thermal vias.

Figure 36. Thermal Resistance vs PCB Area

PCB Layout Considerations

PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance

of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss

in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.

Good layout can be implemented by following a few simple design rules.

1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched

rapidly. The first loop starts from the input capacitor, to the regulator VIN pin, to the regulator SW pin, to the

inductor then out to the output capacitor and load. The second loop starts from the output capacitor ground, to

the regulator PGND pins, to the inductor and then out to the load (see Figure 37). To minimize both loop areas

the input capacitor should be placed as close as possible to the PVIN pin. Grounding for both the input and

output capacitor should consist of a small localized top side plane that connects to PGND and the die attach pad

(DAP). The inductor should be placed as close as possible to the SW pin and output capacitor.

Copyright © 2008–2013, Texas Instruments Incorporated

Submit Documentation Feedback

21

Product Folder Links: LM20146