SCLK

SCSb

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

R/Wb

A3

A2

A1

A0

0

0

0

D7

D6

D5

D4

D3

D2

D1

D0

C7

C6

C5

C4

C3

C2

C1

C0

DDATA FIELDD

Reserved (3-bits)

(MSB)

(LSB)

DCOMMAND FIELDD

Address (4-bits)

Write DATA

SDI

SDO

Hi-Z

D7

D6

D5

D4

D3

D2

D1

D0

(MSB)

(LSB)

Data (8-bits)

Read DATA

DSingle Access CycleD

SVA-30206512

LMH6523

www.ti.com

SNOSC88 – DECEMBER 2012

The enable pins are active in the serial mode to allow rapid power control. This can allow significant power

savings in applications like time division duplex receivers. It is not possible to disable the amplifiers using the SPI

bus, likewise the power control is not available on the SPI bus.

The CLK pin is the serial clock pin. It is used to register the input data that is presented on the SDI pin on the

rising edge; and to source the output data on the SDO pin on the falling edge. User may disable clock and hold it

in the low state, as long as the clock pulse-width minimum specification is not violated when the clock is enabled

or disabled.

The CSb pin is the chip select pin. The b indicates that this pin is actually a “NOT chip select” since the chip is

selected in the logic low state. Each assertion starts a new register access – i.e., the SDATA field protocol is

required. The user is required to deassert this signal after the 16th clock. If the CSb pin is deasserted before the

16th clock, no address or data write will occur. The rising edge captures the address just shifted-in and, in the

case of a write operation, writes the addressed register. There is a minimum pulse-width requirement for the

deasserted pulse – which is specified in the Electrical Specifications section.

The SDI pin is the input pin for the serial data. It must observe setup / hold requirements with respect to the

SCLK. Each cycle is 16-bits long.

The SDO pin is the data output pin. This output is normally at a high impedance state, and is driven only when

CSb is asserted. Upon CSb assertion, contents of the register addressed during the first byte are shifted out with

the second 8 SCLK falling edges. Upon power-up, the default register address is 00h. The SDO pin requires

external bias for clock speeds over 1MHz. See Figure 53 for details on sizing the external bias resistor. Because

the SDO pin is a high impedance pin, the board capacitance present at the pin will restrict data out speed that

can be achieved. For a RC limited circuit the frequency is ~ 1/ (2×Pi×RC). As shown in the figure resistor values

of 300 to 2000 Ohms are recommended.

Each serial interface access cycle is exactly 16 bits long as shown in Figure 52. Each signal's function is

described below. the read timing is shown in Figure 54, while the write timing is shown in Figure 55.

Figure 52. Serial Interface Protocol (SPI compatible)

Copyright © 2012, Texas Instruments Incorporated

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