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LNK3205P/G/D Scheda tecnica(PDF) 3 Page - Power Integrations, Inc. |
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LNK3205P/G/D Scheda tecnica(HTML) 3 Page - Power Integrations, Inc. |
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3 / 28 page ![]() Rev. Q 06/23 3 LinkSwitch-TN2 www.power.com LinkSwitch-TN2 Functional Description LinkSwitch-TN2 combines a high-voltage power MOSFET switch with a power supply controller in one device. Unlike conventional PWM (pulse width modulator) controllers, LinkSwitch-TN2 uses a simple ON/OFF control to regulate the output voltage. The LinkSwitch-TN2 controller consists of an oscillator, feedback (sense and logic) circuit, 5.0 V regulator, BYPASS pin undervoltage circuit, over-temperature protection, line and output overvoltage protection, frequency jittering, current limit circuit, leading edge blanking and a 725 V or 900 V power MOSFET. The LinkSwitch-TN2 incorporates additional circuitry for auto-restart. Oscillator The typical oscillator frequency is internally set to an average of f OSC (66 kHz). Two signals are generated from the oscillator: the maximum duty cycle signal (DC (MAX)) and the clock signal that indicates the beginning of each cycle. The LinkSwitch-TN2 oscillator incorporates circuitry that introduces a small amount of frequency jitter, typically 4 kHz peak-to-peak, to minimize EMI emission. The modulation rate of the frequency jitter is set to 1 kHz to optimize EMI reduction for both average and quasi- peak emissions. The frequency jitter should be measured with the oscilloscope triggered at the falling edge of the DRAIN waveform. The waveform in Figure 5 illustrates the frequency jitter of the LinkSwitch-TN2. Soft-Start At power-up or during a restart attempt in auto-restart, the device applies a soft-start by temporarily reducing the oscillator frequency. LNK3202-07 and LNK329x reduce the frequency to f OSC(SS) (typically 33 kHz. LNK3208 and LNK3209 reduce the oscillator frequency to initially 16.5 kHz followed by a stepwise increase to 22 kHz and 33 kHz over a period of 256 switching cycles. Soft-start terminates and the device continues operating at the nominal oscillator frequency f OSC either after 256 switching cycles or if the output voltage reaches regulation. Feedback Input Circuit The feedback input circuit at the FEEDBACK pin consists of a low impedance source follower output set at V FB (2.0 V). When the current delivered into this pin exceeds I FB (49 μA), a low logic level (disable) is generated at the output of the feedback circuit. This output is sampled at the beginning of each cycle on the rising edge of the clock signal. If high, the power MOSFET is turned on for that cycle (enabled), otherwise the power MOSFET remains off (disabled). The sampling is done only at the beginning of each cycle. Subse- quent changes in the FEEDBACK pin voltage or current during the remainder of the cycle do not impact the MOSFET enable/disable status. If a current greater than I FBSD is injected into the feedback pin while the MOSFET is enabled for at least two consecutive cycles the part will stop switching and enter auto-restart off-time. Normal switching resumes after the auto-restart off-time expires. This shutdown function allows implementing line overvoltage protection in flyback converters (see Figure 6). The current into the FEEDBACK pin should be limited to less than 1.2 mA. 5.0 V Regulator and 5.2 V Shunt Voltage Clamp The 5.0 V regulator charges the bypass capacitor connected to the BYPASS pin to V BP by drawing a current from the voltage on the DRAIN, whenever the MOSFET is off. The BYPASS pin is the internal supply voltage node for the LinkSwitch-TN2. When the MOSFET is on, the LinkSwitch-TN2 runs off of the energy stored in the bypass capacitor. Extremely low power consumption of the internal circuitry allows the LinkSwitch-TN2 to operate continuously from the current drawn from the DRAIN pin. A bypass capacitor value of 0.1 μF is sufficient for both high frequency decoupling and energy storage. In addition, there is a shunt regulator clamping the BYPASS pin at V BP(SHUNT) (5.2 V) when current is provided to the BYPASS pin through an external resistor. This facilitates powering of LinkSwitch-TN2 externally through a bias winding to decrease the no-load consump- tion to about 10 mW (flyback). The device stops switching instantly and enters auto-restart when a current ≥I BPSD is delivered into the BYPASS pin. Adding an external Zener diode from the output voltage to the BYPASS pin allows implementing an hysteretic OVP function in a flyback converter (see Figure 6). The current into the BYPASS pin should be limited to less than 16 mA. BYPASS Pin Undervoltage The BYPASS pin undervoltage circuitry disables the power MOSFET when the BYPASS pin voltage drops below V BP–VBPH (approximately 4.5 V). Once the BYPASS pin voltage drops below this threshold, it must rise back to V BP to enable (turn-on) the power MOSFET. Over-Temperature Protection The thermal shutdown circuitry senses the die temperature. The threshold is set at T SD (142 °C typical) with a 75 °C (TSDH) hysteresis. When the die temperature rises above T SD the power MOSFET is disabled and remains disabled until the die temperature falls to T SD–TSDH, at which point it is re-enabled. Current Limit The current limit circuit senses the current in the power MOSFET. When this current exceeds the internal threshold (I LIMIT), the power MOSFET is turned off for the remainder of that cycle. The leading edge blanking circuit inhibits the current limit comparator for a short time (t LEB) after the power MOSFET is turned on. This leading edge blanking time has been set so that current spikes caused by capaci- tance and rectifier reverse recovery time will not cause premature termination of the switching pulse. Current limit can be selected using the BYPASS pin capacitor (0.1 μF for normal current limit / 1 μF for reduced current limit). LinkSwitch-TN2 selects between normal and reduced current limit at power-up prior to switching. Auto-Restart In the event of a fault condition such as output overload, output short, or an open-loop condition, LinkSwitch-TN2 enters into auto-restart operation. An internal counter clocked by the oscillator gets reset every time the FEEDBACK pin is pulled high. If the FEEDBACK pin is not pulled high for t AR(ON) (50 ms), the power MOSFET switching is disabled for a time equal to the auto-restart off-time. The first time a fault is asserted the off-time is 150 ms 600 020 68 kHz 64 kHz VDRAIN Time ( µs) 500 400 300 200 100 0 Figure 5. Frequency Jitter. |
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