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LP8552 Scheda tecnica(PDF) 39 Page - Texas Instruments

Il numero della parte LP8552
Spiegazioni elettronici  LP8552 High-Efficiency LED Backlight Driver For Notebooks
PDF  49 Pages
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Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
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LP8552 Scheda tecnica(HTML) 39 Page - Texas Instruments

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MCU
LP8552
SW
FB
VLDO
GNDs
EN
ISET
VDDIO
PWM
SCLK
SDA
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
L1
D1
2.7V ± 22V
FILTER
+5V input rail
FSET
15 éH
VSYNC
COUT
CIN
10 éF
4.7 éF
CVLDO
1 éF
VDDIO reference voltage
VSYNC signal
120 k
#
100 nF
RISET
1 éF
FAULT
Can be left floating
if not used
39 pF
VIN
RFSET
VBATT 5.5V ± 22V
10 ± 40V, 180 ± 400 mA
10 ± 25V, 180 mA
LP8552
www.ti.com
SNVS693E – SEPTEMBER 2011 – REVISED SEPTEMBER 2014
Figure 31. Typical Application for Low Input Voltage
NOTE
Separate 5-V rail to VLDO can be also used to improve efficiency for applications with
higher battery voltage. No power sequencing requirements between VIN/VLDO and VBATT.
9.2.2.1 Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range, VBATT
2.7 V to VOUT
5-V input rail, VLDO/VIN
4.5 V to 5.5 V, 10 mA
Brightness Control
PWM input duty cycle (default), I2C can be used as well
PWM output frequency
With RFSET resistor 85 kΩ to100 kΩ; 9.8 kHz with PSPWM enabled
LED Current
With RISET resistor 15 kΩ; 25 mA/channel
Brightness slopes
200-ms linear slope + advanced slope
External set resistors
Enabled
Inductor
10 µH to 33 µH, with 2.5-A saturation current
Boost SW frequency
625 kHz
SW current limit
2.5 A
9.2.2.2 Detailed Design Procedure
Component selection follows Design Requirements above. VLDO capacitor voltage rating can be set based on the
5-V rail voltage specification, which must be < 5.5 V in all cases. Note that UVLO is detected from the VIN pin
voltage, not from the VBATT voltage.
9.2.2.3 Application Curves
Typical Boost and LED current behavior is seen in the Application Curves section.
9.2.3 Typical Application for Three Channels and Low Input Voltage
LED outputs can be connected together to be able to drive three channels with possibly higher output current. To
maintain the optimum phase shifting OUT1 should be paralleled with OUT4, OUT2 with OUT5, and OUT3 with
OUT6.
Copyright © 2011–2014, Texas Instruments Incorporated
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