8.2.1 Design Requirements

• VCC minimum is 3 V and maximum is 5.5V.

• Maximum recommended bit rate is 250 kbit/s.

8.2.2 Detailed Design Procedure

• All DIN, FORCEOFF and FORCEON inputs must be connected to valid low or high logic levels.

• Select capacitor values based on VCC level for best performance.

8.2.3 Application Curves

VCC= 3.3 V

±9

±8

±7

±6

±5

±4

±3

±2

±1

0

1

2

3

4

5

6

0

1

2

3

4

5

6

7

Time ( s)

DIN

DOUT to RIN

ROUT

C001

Figure 8-2. Driver to Receiver Loopback Timing Waveform

8.3 Power Supply Recommendations

VCC should be between 3V and 5.5V. Charge pump capacitors should be chosen using table in Figure 8-1.

8.4 Layout

8.4.1 Layout Guidelines

Keep the external capacitor traces short. This is more important on C1 and C2 nodes that have the fastest rise

and fall times.

In the Layout Example diagram, only critical layout sections are shown. Input and output traces will vary in shape

and size depending on the customer application. FORCEON and FORCEOFF should be pulled up to VCC or

GND via a pullup resistor, depending on which configuration the user desires upon power-up.

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MAX3243

SLLS350Q – APRIL 1999 – REVISED AUGUST 2024

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