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TPS22918DBVT Scheda tecnica(PDF) 21 Page - Texas Instruments |
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TPS22918DBVT Scheda tecnica(HTML) 21 Page - Texas Instruments |
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21 / 30 page ![]() J(MAX) A D(MAX) JA T T P - = q 1 VOUT 2 QOD 3 CT 4 ON 5 GND 6 VIN VIA to Power Ground Plane 21 TPS22918 www.ti.com SLVSD76C – FEBRUARY 2016 – REVISED JULY 2017 Product Folder Links: TPS22918 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated 11.2 Layout Example Figure 32. Recommended Board Layout 11.3 Thermal Considerations For best performance, all traces must be as short as possible. To be most effective, the input and output capacitors must be placed close to the device to minimize the effects that parasitic trace inductances may have on normal and short-circuit operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects along with minimizing the case to ambient thermal impedance. The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. To calculate the maximum allowable dissipation, PD(max) for a given output current and ambient temperature, use Equation 14: where • PD(MAX) = maximum allowable power dissipation • TJ(MAX) = maximum allowable junction temperature (125°C for the TPS22918) • TA = ambient temperature of the device • θJA = junction to air thermal impedance. Refer to the Thermal Information table. This parameter is highly dependent upon board layout. (14) |
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