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DAC8564 Scheda tecnica(PDF) 31 Page - Texas Instruments

Il numero della parte DAC8564
Spiegazioni elettronici  16-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output Digital-to-Analog Converter with 2.5V, 2ppm/°C Internal Reference
PDF  51 Pages
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Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
Logo TI2 - Texas Instruments

DAC8564 Scheda tecnica(HTML) 31 Page - Texas Instruments

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DAC8565
www.ti.com
SBAS411C
– JUNE 2007 – REVISED MARCH 2011
OPERATING EXAMPLES: DAC8565
For the following examples, X = don't care. Value can be either '0' or '1'.
Example 1: Write to Data Buffer A Through Buffer D; Load DAC A Through DAC D Simultaneously
•
1st: Write to data buffer A:
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
–DB0
(LD1)
(LD0)
(DAC Sel 1) (DAC Sel 0)
(PD0)
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
–D0
•
2nd: Write to data buffer B:
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
–DB0
(LD1)
(LD0)
(DAC Sel 1) (DAC Sel 0)
(PD0)
0
0
0
0
0
0
1
0
D15
D14
D13
D12
D11
–D0
•
3rd: Write to data buffer C:
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
–DB0
(LD1)
(LD0)
(DAC Sel 1) (DAC Sel 0)
(PD0)
0
0
0
0
0
1
0
0
D15
D14
D13
D12
D11
–D0
•
4th: Write to data buffer D and simultaneously update all DACs:
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
–DB0
(LD1)
(LD0)
(DAC Sel 1) (DAC Sel 0)
(PD0)
0
0
1
0
0
1
1
0
D15
D14
D13
D12
D11
–D0
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon
completion of the 4th write sequence. (The DAC voltages update simultaneously after the 24th SCLK falling edge
of the fourth write cycle).
Example 2: Load New Data to DAC A Through DAC D Sequentially
•
1st: Write to data buffer A and load DAC A: DAC A output settles to specified value upon completion:
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
–DB0
(LD1)
(LD0)
(DAC Sel 1) (DAC Sel 0)
(PD0)
0
0
0
1
0
0
0
0
D15
D14
D13
D12
D11
–D0
•
2nd: Write to data buffer B and load DAC B: DAC B output settles to specified value upon completion:
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
–DB0
(LD1)
(LD0)
(DAC Sel 1) (DAC Sel 0)
(PD0)
0
0
0
1
0
0
1
0
D15
D14
D13
D12
D11
–D0
•
3rd: Write to data buffer C and load DAC C: DAC C output settles to specified value upon completion:
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
–DB0
(LD1)
(LD0)
(DAC Sel 1) (DAC Sel 0)
(PD0)
0
0
0
1
0
1
0
0
D15
D14
D13
D12
D11
–D0
•
4th: Write to data buffer D and load DAC D: DAC D output settles to specified value upon completion:
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
–DB0
(LD1)
(LD0)
(DAC Sel 1) (DAC Sel 0)
(PD0)
0
0
0
1
0
1
1
0
D15
D14
D13
D12
D11
–D0
After completion of each write cycle, DAC analog output settles to the voltage specified.
Copyright
© 2007–2011, Texas Instruments Incorporated
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