1

FEATURES

APPLICATIONS

DESCRIPTION

1 2 − B it

A D C

P L L

S/H

S eria lize r

1 x A D C LK

6 x A D C LK

IN 1

P

A D C L K

IN 1

N

O U T 1

P

O U T 1

N

1 2 − B it

A D C

S/H

S eria lize r

IN 2

P

IN 2 N

O U T 2

P

O U T 2

N

1 2 − B it

A D C

S/H

S eria lize r

IN 3

P

IN 3

N

O U T 3

P

O U T 3

N

L CL K

P

L CL K

N

A D C LK

P

A D C LK

N

1 2 x A D CL K

1 2 − B it

A D C

S/H

S eria lize r

IN 4 P

IN 4

N

O U T 4P

O U T 4

N

1 2 − B it

A D C

S/H

S eria lize r

IN 5

P

IN 5

N

O U T 5

P

O U T 5

N

1 2 − B it

A D C

S/H

S eria lize r

IN 6

P

IN 6 N

O U T 6

P

O U T 6

N

1 2 − B it

A D C

S/H

S eria lize r

IN 7

P

IN 7

N

O U T 7

P

O U T 7

N

1 2 − B it

A D C

S/H

S eria lize r

Re feren ce

IN 8

P

IN 8

N

IN T /E X T

O U T 8

P

O U T 8

N

R e g isters

C on trol

ADS5272

www.ti.com...................................................................................................................................................... SBAS324C – JUNE 2004 – REVISED JANUARY 2009

8-Channel, 12-Bit, 65MSPS ADC

with Serial LVDS Interface

An integrated phase lock loop (PLL) multiplies the

incoming ADC sampling clock by a factor of 12. This

23

• Maximum Sample Rate: 65MSPS

high-frequency LVDS clock is used in the data

• 12-Bit Resolution

serialization and transmission process. The word

output of each internal ADC is serialized and

• No Missing Codes

transmitted either MSB or LSB first. In addition to the

• Total Power Dissipation:

eight data outputs, a bit clock and a word clock are

Internal Reference: 983mW

also transmitted. The bit clock is at 6x the speed of

External Reference: 917mW

the sampling clock, whereas the word clock is at the

• CMOS Technology

same speed of the sampling clock.

• Simultaneous Sample-and-Hold

The ADS5272 provides internal references, or can

• 71.1dBFS SNR at 5MHz IF

optionally be driven with external references. Best

performance

is

achieved

through

the

internal

• 3.3V Digital/Analog Supply

reference mode.

• Serialized LVDS Outputs

The device is available in a TQFP-80 PowerPAD

• Integrated Frame and Bit Patterns

package and is specified over a –40°C to +85°C

• Option to Double LVDS Clock Output Currents

operating range.

• Four Current Modes for LVDS

• Pin- and Format-Compatible Family

• TQFP-80 PowerPAD™ Package

• Portable Ultrasound Systems

• Tape Drives

• Test Equipment

• Optical Networking

The ADS5272 is a high-performance, 65MSPS,

8-channel analog-to-digital converter (ADC). Internal

references are provided, simplifying system design

requirements. Low power consumption allows for the

highest of system integration densities. Serial LVDS

(low-voltage differential signaling) outputs reduce the

number of interface lines and package size.

RELATED PRODUCTS

RESOLUTION

SAMPLE

MODEL

(BITS)

RATE (MSPS)

CHANNELS

ADS5270

12

40

8

ADS5271

12

50

8

ADS5273

12

70

8

ADS5277

10

65

8

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

PowerPAD is a trademark of Texas Instruments.

3

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2004–2009, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.