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ADS1232IPWR Scheda tecnica(PDF) 21 Page - Texas Instruments

Il numero della parte ADS1232IPWR
Spiegazioni elettronici  ADS123x 2- and 4-Channel, 24-Bit, Delta-Sigma ADCs for Bridge Sensors
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7.3.7 Settling Time
After changing the input multiplexer, the first data are fully settled. In both ADS123x devices, the digital filter is
allowed to settle after toggling either the A1 or A0 pin. Toggling any of these digital pins holds the DRDY/DOUT
line high until the digital filter is fully settled. For example, if A0 changes from low to high, selecting a different
input channel, DRDY/DOUT immediately goes high, and DRDY/DOUT goes low when fully settled data are
ready for retrieval. There is no need to discard any data. Figure 7-7 shows the timing of the DRDY/DOUT line as
the input multiplexer changes.
In certain instances, large or abrupt input changes require four data cycles to settle. One example of such a
change is an external multiplexer in front of the ADS123x, which can cause large changes in input voltage simply
by switching input channels. Another example is toggling the TEMP pin, which switches the internal AINP, AINN
signals to connect to either the external AINPx, AINNx pins or to the TEMP diode (see Figure 7-1).
To acquire fully settled data after an input step change, five readings are required. Five readings are required
because if the change in input occurs in the middle of the first conversion, four additional full conversions of the
fully settled input are required to get fully settled data. Discard the first four readings because they contain only
partially settled data. Figure 7-8 illustrates the settling time for the ADS123x in continuous conversion mode.
A1orA0
t
1
DRDY/DOUT
t
S
Figure 7-7. Example of Settling Time After Changing the Input Multiplexer
Table 7-5. Timing Requirements for Figure 7-7
PARAMETER(1)
MIN
MAX
UNIT
tS
Setup time for changing the A1 or A0 pins
40
50
μs
t1
Settling time (DRDY/DOUT
held high)
SPEED = 1
51
51
ms
SPEED = 0
401
401
ms
(1)
Values given for fCLK = 4.9152 MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
ToggledTEMPPinor AbruptChangeinExternalV
IN
V
IN
DRDY/DOUT
Startof
conversion.
1stconversion;
includes
unsettledV .
IN
2ndconversion;
V
settled,but
IN
digitalfilter
unsettled.
3rdconversion;
V
settled,but
IN
digitalfilter
unsettled.
4thconversion;
V
settled,but
IN
digitalfilter
unsettled.
5thconversion;
V
anddigital
IN
filterboth
settled.
Conversion
Time
Figure 7-8. Settling Time in Continuous Conversion Mode
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ADS1232, ADS1234
SBAS350H – JUNE 2005 – REVISED JUNE 2025
Copyright © 2025 Texas Instruments Incorporated
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