P

S

P

SCLK

SDATA

A

Bit 7 (MSB)

Bit 6

Bit 0 (LSB)

th(SDATA)

tsu(SDATA)

tsu(START)

t(BUS)

th(START)

tr(SM)

tr(SM)

tf(SM)

tf(SM)

tW(SCLH)

tW(SCLL)

tsu(STOP)

VIH(SM)

VIL(SM)

VIH(SM)

VIL(SM)

Not Recommended for New Designs

CDC706

SCAS829B – SEPTEMBER 2006 – REVISED FEBRUARY 2008...................................................................................................................................... www.ti.com

Byte Write Programming Sequence

1

7

1

1

8

1

8

1

1

S

Slave Address

Wr

A

CommandCode

A

Data Byte

A

P

Figure 7. Byte Write Protocol

Byte Read Programming Sequence

1

7

1

1

8

1

1

7

1

1

S

Slave Address

Wr

A

CommandCode

A

S

Slave Address

Rd

A

8

1

1

Data Byte

A

P

Figure 8. Byte Read Protocol

Block Write Programming Sequence

(1)

1

7

1

1

8

1

8

1

S

Slave Address

Wr

A

CommandCode

A

Byte Count N

A

8

1

8

1

8

1

1

Data Byte 0

A

Data Byte 1

A

- - - - -

Data Byte N–1

A

P

(1)Data Byte 0 is reserved for revision code and vendor identification. However, this byte is used for internal test. Do not write into it other

than 0000 0000.

Figure 9. Block Write Protocol

Block Read Programming Sequence

1

7

1

1

8

1

1

7

1

1

S

Slave Address

Wr

A

CommandCode

A

Sr

Slave Address

Rd

A

8

1

8

1

8

1

1

Byte Count N

A

Data Byte 0

A

- - - - -

Data Byte N–1

A

P

Figure 10. Block Read Protocol

Figure 11. Timing Diagram Serial Control Interface

12

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