CDCE925PW datasheet(26/40 Pages) TI2

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if P

0 then P = 0

Q= int

R = N'

4 int log

= -

CDCE925, CDCEL925

SCAS847I – JULY 2007 – REVISED OCTOBER 2016

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Product Folder Links: CDCE925 CDCEL925

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Typical Application (continued)

The PLL internally operates as fractional divider and needs the following multiplier/divider settings:

where

•

′ = N × 2

•

≥ M

•

80 MHz

≤ ƒVCO ≤ 230 MHz

•

≤ q ≤ 63

•

≤ p ≤ 4

•

≤ r ≤ 511

(3)

Example:

for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2;

for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2;

→ fOUT = 54 MHz

→ fOUT = 74.25 MHz

→ fVCO = 108 MHz

→ fVCO = 148.50 MHz

→ P = 4 – int(log24) = 4 – 2 = 2

→ P = 4 – int(log25.5) = 4 – 2 = 2

→ N′’ = 4 × 22 = 16

→ N′’ = 11 × 22 = 44

→ Q = int(16) = 16

→ Q = int(22) = 22

→ R = 16 – 16 = 0

→ R = 44 – 44 = 0

The values for P, Q, R, and N’ are automatically calculated when using TI Pro-Clock™ software.

10.2.2.3 Crystal Oscillator Start-Up

When the CDCEx925 is used as a crystal buffer, crystal oscillator start-up dominates the start-up time compared

to the internal PLL lock time. The following diagram shows the oscillator start-up sequence for a 27-MHz crystal

input with an 8-pF load. The start-up time for the crystal is in the order of approximately 250 µs compared to

approximately 10 µs of lock time. In general, lock time is an order of magnitude less compared to the crystal

start-up time.

Figure 18. Crystal Oscillator Start-Up vs PLL Lock Time

10.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling

The frequency for the CDCEx925 is adjusted for media and other applications with the VCXO control input VCtrl.

If a PWM modulated signal is used as a control signal for the VCXO, an external filter is needed.

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