DLP2000 datasheet(3/37 Pages) TI2

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5 Pin Configuration and Functions

Figure 5-1. FQC Package 42-Pin LGA Bottom View

Table 5-1. Pin Functions

TYPE

SIGNAL

DATA

RATE

DESCRIPTION

PACKAGE NET

LENGTH (mm)

NAME

NO.

DATA INPUTS

DATA(0)

J13

Input

LVCMOS

DDR

Input data bus

8.83

DATA(1)

Input

LVCMOS

DDR

Input data bus

7.53

DATA(2)

Input

LVCMOS

DDR

Input data bus

6.96

DATA(3)

Input

LVCMOS

DDR

Input data bus

7.05

DATA(4)

Input

LVCMOS

DDR

Input data bus

7.56

DATA(5)

Input

LVCMOS

DDR

Input data bus

7.07

DATA(6)

J12

Input

LVCMOS

DDR

Input data bus

7.61

DATA(7)

J10

Input

LVCMOS

DDR

Input data bus

7.68

DATA(8)

Input

LVCMOS

DDR

Input data bus

7.31

DATA(9)

Input

LVCMOS

DDR

Input data bus

6.76

DATA(10)

Input

LVCMOS

DDR

Input data bus

8.18

DATA(11)

Input

LVCMOS

DDR

Input data bus

7.81

DCLK

Input

LVCMOS

Input data clock

7.78

CONTROL INPUTS

LOADB

K10

Input

LVCMOS

DDR

Parallel latch load enable

7.64

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DLP2000

DLPS140B – MARCH 2019 – REVISED MAY 2022

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