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PCF8545ATT/A Scheda tecnica(PDF) 52 Page - NXP Semiconductors |
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PCF8545ATT/A Scheda tecnica(HTML) 52 Page - NXP Semiconductors |
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52 / 72 page ![]() PCF8545 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 1 — 13 November 2013 52 of 72 NXP Semiconductors PCF8545 Universal LCD driver for multiplex rates up to 1:8 Fig 43. I2C-bus timing waveforms Table 36. Timing characteristics: SPI-bus VDD = 1.8 V to 5.5 V; VSS =0V; Tamb = 40 C to +85 C. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and VIH with an input voltage swing of VSS to VDD. Timing waveforms see Figure 44. Symbol Parameter Conditions VDD < 2.7 V VDD 2.7 V Unit Min Max Min Max fclk(SCL) SCL clock frequency - 2 - 5 MHz tSCL SCL time 500 - 200 - ns tclk(H) clock HIGH time 200 - 80 - ns tclk(L) clock LOW time 200 - 80 - ns tr rise time for SCL signal - 100 - 100 ns tf fall time for SCL signal - 100 - 100 ns tsu(CE_N) CE_N set-up time 150 - 80 - ns th(CE_N) CE_N hold time 0 - 0 - ns trec(CE_N) CE_N recovery time 100 - 100 - ns tsu set-up time set-up time for SDI data 10 -5 -ns th hold time hold time for SDI data 25 - 10 - ns |
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