DocID026048 Rev 2

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SR1

Timing diagrams

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Timing diagrams

Figure 7. RST output without tREC option

1.

VCC should be powered up before or together with voltage on the SR input to prevent entering test mode

by creating

a condition V(SR) > VCC +1.1 V typ.

Figure 8. RST output with tREC option

1.

VCC should be powered up before or together with voltage on the SR input to prevent entering test mode

by creating

a condition V(SR) > VCC +1.1 V typ.