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LP5030 Scheda tecnica(PDF) 58 Page - Texas Instruments |
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LP5030 Scheda tecnica(HTML) 58 Page - Texas Instruments |
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58 / 61 page ![]() www.ti.com PACKAGE OUTLINE C 46X 0.25 0.15 2.8 0.05 46X 0.45 0.25 1 MAX (0.2) TYP 0.05 0.00 42X 0.4 2X 4.8 2X 3.6 3.8 0.05 A 5.1 4.9 B 6.1 5.9 VQFN - 1 mm max height RJV0046A PLASTIC QUAD FLATPACK - NO LEAD 4223948/B 01/2018 PIN 1 INDEX AREA 0.08 C SEATING PLANE 1 13 24 36 14 23 46 37 PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 47 SCALE 2.500 |
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