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LP8754 Scheda tecnica(PDF) 17 Page - Texas Instruments |
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LP8754 Scheda tecnica(HTML) 17 Page - Texas Instruments |
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17 / 52 page ![]() LOAD CURRENT N=1 BEST EFFICIENCY OBTAINED WITH N=2 N=3 N=4 N=5 N=6 + - FBP FBN DIFFERENTIAL TO SINGLE-ENDED + - + - POWER GOOD LOOP COMP RAMP GENERATOR PMOS CURRENT SENSE NMOS CURRENT SENSE GATE CONTROL IADC VDAC ERROR AMP GND NEG CURRENT LIMIT ZERO CROSS DETECT SW POS CURRENT LIMIT VIN VOUT CONTROL BLOCK PROGRAMMABLE PARAMETERS SLAVE INTERFACE VOLTAGE SETTING SLEW RATE CONTROL SLAVE PHASE CONTROL MASTER INTERFACE LP8754 www.ti.com SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 Features Descriptions (continued) Figure 8. Detailed Block Diagram Showing One Buck Core 7.3.1.1 Multi-Phase Operation and Phase-Shedding Under heavy load conditions, the switching phase of the bucks are interleaved. As a result, the 6-phase converter has higher effective switching frequency than the switching frequency of any one phase. The parallel operation decreases the efficiency at low load conditions. In order to overcome this operational inefficiency, the LP8754 automatically changes the number of active phases to maximize the efficiency. This is called phase-shedding and the concept is illustrated in Figure 9. Figure 9. Multi-phase Buck Converter Efficiency vs Number of Phases; All Converters in PWM Mode (1) (1) Graph is not to scale and is for illustrative purposes only. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: LP8754 |
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