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Advanced CMOS TTL Input – 54ACT00

Quad 2-Input NAND Gate in bare die form



Inputs directly accept TTL



Outputs directly interface CMOS, NMOS and TTL



Outputs Source/Sink 24 mA



Low Input Current: 1µA



Full Military Temperature Range



Lower power alternative to bipolar logic



Functionally compatible with bipolar 54LS00



Upgrade for 54HCT00.

Rev 2.0

23/09/25

Features:

Ordering Information

The following part suffixes apply:



No suffix - MIL-STD-883 /2010B Visual Inspection



“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT



“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

For further information on LAT process flows see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification



Default – Die in Waffle Pack (400 per tray capacity)



Sawn Wafer on Tape – On request



Unsawn Wafer – On request



Die Thickness <> 280µm(11 Mils) – On request



Assembled into Ceramic Package – On request

Description

Die Dimensions in µm (mils)

The 54ACT00 quad 2-input NAND gate is fabricated

using an advanced 5V CMOS process combining high

speed LSTTL performance with CMOS low power. The

device consists of x4 independent 2-input NAND gates

performing the Boolean function Y = A • B or Y = A + B.

Internal circuitry comprises of three stages and includes

buffered output for high noise immunity and stability.

Inputs are directly compatible with LSTTL outputs. All

inputs are protected against ESD and excess voltage

transients.

Die Size (Unsawn)

530 x 660

21 x 26

µm

mils

Minimum Bond Pad Size

76 x 76

3 x 3

µm

mils

Die Thickness

280 (±20)

11.02 (±0.79)

µm

mils

Top Metal Composition

Al-Si-Cu

Back Metal Composition

N/A – Bare Si

530 (21)