Nexperia

PUSB3FA0

ESD protection for ultra high-speed interfaces

PUSB3FA0

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© Nexperia B.V. 2018. All rights reserved.

Product data sheet

Rev. 1 — 1 February 2018

8 / 12

VCL (V)

0

6

4

2

aaa-009371

2

4

6

IPP

(A)

0

IEC 61000-4-5; tp = 8/20 μs; positive pulse

Figure 11. Dynamic resistance with positive clamping;

typical values

VCL (V)

-2.5

0

-0.5

-1.5

-1.0

-2.0

aaa-009372

-4

-2

0

IPP

(A)

-6

IEC 61000-4-5; tp = 8/20 μs; negative pulse

Figure 12. Dynamic resistance with negative clamping;

typical values

VCL (V)

0

12

8

4

aaa-009373

14

I

(A)

0

2

4

6

8

10

12

tp = 100 ns; Transmission Line Pulse (TLP)

Figure 13. Dynamic resistance with positive clamping;

typical values

VCL (V)

-6

0

-2

-4

aaa-009374

0

I

(A)

-14

-12

-10

-8

-6

-4

-2

tp = 100 ns; Transmission Line Pulse (TLP)

Figure 14. Dynamic resistance with negative clamping;

typical values

The device uses an advanced clamping structure showing a negative dynamic

resistance. This snap-back behavior strongly reduces the clamping voltage to the system

behind the ESD protection during an ESD event. Do not connect unlimited DC current

sources to the data lines to avoid keeping the ESD protection device in snap-back state

after exceeding breakdown voltage (due to an ESD pulse for instance).