www.ti.com

0.01

µF

0.01

µF

CLKP

CLKM

Square Wave

or Sine Wave

(3V

PP)

ADS5510

0.01

µF

CLKP

CLKM

0.01

µF

Differential Square Wave

or Sine Wave

(3V

PP)

ADS5510

INTERNAL DLL

OUTPUT INFORMATION

ADS5510

SLAS499 – JANUARY 2007

Figure 31. AC-Coupled, Single-Ended Clock Input

The ADS5510 clock input can also be driven differentially, reducing susceptibility to common-mode noise. In this

case, it is best to connect both clock inputs to the differential input clock signal with 0.01-

µF capacitors, as

shown in Figure 32.

Figure 32. AC-Coupled, Differential Clock Input

For high input frequency sampling, it is recommended to use a clock source with low jitter. Additionally, the

internal ADC core uses both edges of the clock for the conversion process. This means that, ideally, a 50% duty

cycle should be provided. Figure 19 shows the performance variation of the ADC versus clock duty cycle.

Bandpass filtering of the source can help produce a 50% duty cycle clock and reduce the effect of jitter. When

using a sinusoidal clock, the clock jitter further improves as the amplitude is increased. In that sense, using a

differential clock allows for the use of larger amplitudes without exceeding the supply rails and absolute

maximum ratings of the ADC clock input. Figure 18 shows the performance variation of the device versus input

clock amplitude. For detailed clocking schemes based on transformer or PECL-level clocks, see the

ADS55xxEVM User's Guide (SLWU010), available for download from www.ti.com.

In order to obtain the fastest sampling rates achievable with the ADS5510, the device uses an internal digital

delay lock loop (DLL). Nevertheless, the limited frequency range of operation of DLL degrades the performance

at clock frequencies below 60 MSPS. In order to operate the device below 60 MSPS, the internal DLL must be

shut off using the DLL OFF mode described in the Serial Interface Programming section. The Typical

Performance Curves show the performance obtained in both modes of operation: DLL ON (default) and DLL

OFF. In either of the two modes, the device enters power-down mode if no clock or slow clock is provided. The

limit of the clock frequency where the device functions properly with default settings is ensured to be over 2

MHz.

The ADC provides 11 data outputs (D10 to D0, with D10 being the MSB and D0 the LSB), a data-ready signal

(CLKOUT, pin 43), and an out-of-range indicator (OVR, pin 64) that equals 1 when the output reaches the

full-scale limits.

Two different output formats (straight offset binary or two's complement) and two different output clock polarities

(latching output data on rising or falling edge of the output clock) can be selected by setting DFS (pin 40) to one

of four different voltages. Table 3 details the four modes. In addition, output enable control (OE, pin 41, active

high) is provided to put the outputs into a high-impedance state.

23

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