5

Application information

5.1

Operating voltages

The TSZ151 and TSZ152 devices can operate from 1.8 to 5.5 V. The parameters are fully specified at 1.8 V, 3.3

V, and 5 V power supplies. However, the parameters are very stable over the full VCC range and several

characterization curves show the TSZ151 and TSZ152 devices characteristics over the full operating range.

Additionally, the main specifications are guaranteed in an extended temperature range from -40 to 125 °C.

5.2

Input offset voltage drift vs. temperature

The maximum input voltage drift variation vs. temperature is defined as the offset variation related to the offset

value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and

the amplifier input offset (Vio) is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can

be compensated during production at application level. The maximum input voltage drift vs. temperature enables

the system designer to anticipate the effect of temperature variations. The maximum input voltage drift vs.

temperature is computed using equation 1.

ΔVioΔT= Vio_T−Vio_25°C

T−25°C T=−40°CandT=125°C

(1)

The datasheet minimum and maximum values are guaranteed by a measurement on a representative sample

size ensuring a Cpk (process capability index) greater than 1.3.

5.3

Maximum power dissipation

The usable output load current drive is limited by the maximum power dissipation allowed by the device package.

The absolute maximum junction temperature for the TSZ151 is 150 °C. The junction temperature can be

estimated as follows:

TJ=PD×θJA+TA

(2)

TJ is the die junction temperature.

PD is the power dissipated in the package.

θJA is the junction to thermal resistance of the package.

TA is the ambient temperature.

The power dissipated in the package PD is the sum of the quiescent power dissipated and the power dissipated

by the output stage transistor. It is calculated as follows:

PD = (VCC × ICC) + (VCC+ − VOUT) × IOUT when the op amp is sourcing the current.

PD = (VCC × ICC) + (VOUT − VCC−) × IOUT when the op amp is sinking the current.

Do not exceed the 150 °C maximum junction temperature for the device. Exceeding the junction temperature limit

can cause degradation in the parametric performance or even destroy the device.

5.4

PCB layout recommendations

Particular attention must be paid to the layout of the PCB tracks connected to the amplifier, load, and power

supply. The power and ground traces are critical as they must provide adequate energy and grounding for all

circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic

inductance. In addition, to minimize parasitic impedance over the entire surface, use a multi-via technique that

connects the bottom and top layer ground planes together in many locations. The copper traces that connect the

output pins to the load and supply pins should be as wide as possible to minimize trace resistance.

5.5

Decoupling capacitor

In order to ensure op amp full functionality, it is mandatory to place a decoupling capacitor of at least 22 nF as

close as possible to the op amp supply pin. A good decoupling helps to reduce an electromagnetic interference

impact.

TSZ151, TSZ152

Application information

DS14459 - Rev 4

page 26/39