Device Interface Timings

Table 24: High-speed Device Interface Timing

Parameter

Symbol

Min.

Max.

Unit

Remark

Clock CLK1

Clock frequency Data Transfer Mode (PP)2 fPP

0

523

MHz

CL ≤ 30 pF

Tolerance:+100KHz

Clock frequency Identification Mode (OD) fOD

0

400

kHz

Tolerance: +20KHz

Clock high time

tWH

6.5

ns

CL ≤ 30 pF

Clock low time

tWL

6.5

ns

CL ≤ 30 pF

Clock rise time4

tTLH

3

ns

CL ≤ 30 pF

Clock fall time

tTHL

3

ns

CL ≤ 30 pF

Inputs CMD, DAT (referenced to CLK)

Input set-up time

tISU

3

ns

CL ≤ 30 pF

Input hold time

tIH

3

ns

CL ≤ 30 pF

Outputs CMD, DAT (referenced to CLK)

Output delay time during data transfer

tODLY

13.7

ns

CL ≤ 30 pF

Output hold time

tOH

2.5

ns

CL ≤ 30 pF

Signal rise time5

tRISE

3

ns

CL ≤ 30 pF

Signal fall time

tFALL

3

ns

CL ≤ 30 pF

Note 1: CLK timing is measured at 50% of VDD.

Note 2: eMMC shall support the full frequency range from 0-26MHz or 0-52MHz

Note 3: Device can operate as high-speed Device interface timing at 26 MHz clock frequency.

Note 4: CLK rise and fall times are measured by min (VIH) and max (VIL).

Note 5: Inputs CMD DAT rise and fall times are measured by min (VIH) and max (VIL) and outputs CMD DAT rise and fall times are

measured by min (VOH) and max (VOL).

Confidential

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／42-

Rev.1.0 July 2023

32GB/64GB/128GB eMMC