DAC5578SRGET datasheet(29/60 Pages) TI2

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ChangeofDataAllowed

DataLineStable;

DataValid

SDA

SCL

DAC5578

DAC6578

DAC7578

www.ti.com

SBAS496B – MARCH 2010 – REVISED AUGUST 2012

slave. All I2C-compatible devices recognize the

DACx578 I

2C UPDATE SEQUENCE

stop condition. Upon receipt of a stop condition,

For a single update, the DACx578 requires a start

the bus is released, and all slave devices then

condition, a valid I2C address (A) byte, a command

wait for a start condition followed by a matching

and access (CA) byte, and two data bytes, the most

address.

significant data byte (MSDB) and least significant

data byte (LSDB), as shown in Table 1.

After

each

byte

received,

the

DACx578

acknowledges by pulling the SDA line low during the

high period of a single clock pulse, as shown in

Figure 116. These four bytes and acknowledge

cycles make up the 36 clock cycles required for a

single update to occur. A valid I2C address selects

the

corresponding

slave

device

(for

example,

Figure 115. I2C Bus Bit Transfer

DACx578).

The CA byte sets the operational mode of the

HS Mode Protocol

selected DACx578. When the operational mode is

•

When the bus is idle, both the SDA and SCL lines

selected by this byte, the DACx578 must receive two

are pulled high by the pull-up resistors.

data bytes, the most significant data byte (MSDB)

•

The master generates a start condition followed

and least significant data byte (LSDB), for data

by a valid serial byte containing HS mode master

update to occur. The DACx578 performs an update

code 00001XXX. This transmission is made in F/S

on the falling edge of the acknowledge signal that

mode at no more than 1.0Mbps. No device is

follows the LSDB.

allowed to acknowledge the HS mode master

The CA byte does not have to be re-sent until a

code, but all devices must recognize it and switch

change in operational mode is required. The bits of

the respective internal settings to support 3.4Mbps

the control byte continuously determine the type of

operation.

update performed. Thus, for the first update, the

•

The master then generates a repeated start

DACx578 requires a start condition, a valid I2C

condition (a repeated start condition has the same

address, the CA byte, and two data bytes (MSDB and

timing as the start condition). After this repeated

LSDB). For all consecutive updates, the DACx578

start condition, the protocol is the same as F/S

needs only an MSDB and LSDB, as long as the CA

mode, except that transmission speeds up to

byte command remains the same.

3.4Mbps are allowed. A stop condition ends HS

When using the I2C HS mode (clock = 3.4MHz), each

mode and switches all the internal settings of the

12-bit DAC update other than the first update can be

slave devices to support F/S mode. Instead of

done within 18 clock cycles (MSDB, acknowledge

using a stop condition, repeated start conditions

signal, LSDB, acknowledge signal) at 188.88kSPS.

should be used to secure the bus in HS mode.

When using Fast mode (clock = 400kHz), the

maximum DAC update rate is limited to 22.22kSPS.

Using the Fast mode plus (clock = 1MHz), the

maximum DAC update rate is limited to 55.55kSPS.

When a stop condition is received, the DACx578

releases the I2C bus and awaits a new start condition.

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