L9663 datasheet(35/106 Pages) STMICROELECTRONICS

35 / 106 page

DS11401 Rev 6

35/106

L9663

Satellite interface

105

The interface can be configured both in asynchronous and synchronous mode (in the

second case, the number of bits must be the same for all the timeslots). The accepted

configuration for init data is based on 20 total bits, as follows:



16 data bits



1 status bit



3 frame control

3.4

Upstream data buffer

Basic features:



Adapts the signals delivered by Sync Pulse Timer block in order to make possible a

bidirectional communication ECU to sensor



Generates the trigger signal necessary for an event triggered sync pulse



Provides the Sync Pulse Trigger signal to the Sync Pulse Generator

Figure 20. ECU to sensor communication diagram

The synchronization bits in the ECU to sensor communication must be programmed in the

upstream data buffer by the microcontroller.

The upstream data buffer has 64 bits. The clock for the register is the output of the Sync

Pulse Timer together with the trigger commands via SPI. After each request for a sync

pulse, the register is shifted by one and the last bit is fed into the sync pulse trigger

generator.

Depending on the data length, only a part of the upstream data buffer is used. After the

writing of the relevant part of the buffer, the µC writes the upstream data confirm bit in the

UDBCR register (bit UDBx_RDY). After this confirmation, the trigger source can start the

communication. If these data are sent, the upstream data buffer is ready for new data. This

is indicated by the SPI flag UDBx_BUSY='0'. If new data is written to the buffer while

UDBx_BUSY is still '1', the write command is ignored and the error flag UDBx_FLT is set.

Sync pulse timer

-Timer triggerred mode

SPI sync pulse

masking

Sync pulse

gen.

shift trigger

Upstream databuffer

Sync lenght

Data from microcontroller

SPI event

triggered

Direct IF event

triggered

GAPG2710151614PS

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