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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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L99PM72PXP Scheda tecnica(PDF) 46 Page - STMicroelectronics |
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L99PM72PXP Scheda tecnica(HTML) 46 Page - STMicroelectronics |
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46 / 128 page  Protection and diagnosis L99PM72PXP 46/128 Doc ID 023553 Rev 3 The PWM 1/3 channels start a PWM period with the ON phase, while the PWM 2/4 channels start with the OFF phase. In this way it is possible to use the 4 PWM channels in a phase shifted way. The picture below shows this feature with a duty cycle of 25% for both PWM channels. Figure 24. Phase shifted PWM 3.4 Low side driver outputs REL1, REL2 The outputs REL1, REL2 (RDSon =2 typ. @25 C) are specially designed to drive relay loads. The outputs provide an active output zener clamping (45 V typ.) feature for the demagnetization of the relay coil, even though a load dump condition exists. For Fail_safe reasons the relay drivers are linked with the fail safe operation: In case of entering the Fail Safe Mode, the relay drivers switch off and the SPI control bits are set to default (i.e. driver is off). The low side drivers switch off in case of: ● VS overvoltage and undervoltage ● Overcurrent ● Overtemperature with pre warning OUT3 PWM 3 - OUT4 PWM 4 Timer 2 OUTHS PWM 3 / PWM 4 Timer 1 / Timer 2 Table 8. PWM configuration for high-side outputs (continued) High side output PWM channel Internal timer |
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