L9963E datasheet(128/184 Pages) STMICROELECTRONICS

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Application information

6.1

Layout recommendations

6.1.1

PCB stackup

In order to achieve the best performances in terms of accuracy and EMC, an optimal PCB layer partitioning must

be chosen. ST recommends the following stackup on a 4-layer board:

•

Top layer: analog sense lines (refer to Section 6.1.3 Cell balancing (Force) and cell sensing (Sense) lines)

–

Battery supply and sense line (pin VBAT)

–

Cell voltage sense (pins Cx)

–

Current sense (pins ISENSEx)

–

NTC sense (pins GPIOx)

–

GNDREF

•

2nd layer: ground planes (refer to Section 6.1.2 Ground connections for further details)

–

AGND under sense lines

–

DGND under communication and digital lines

–

GND_ESD/PACK_GND under the ESD caps in the battery connector region

•

3rd layer: analog force lines (refer to Section 6.1.3 Cell balancing (Force) and cell sensing (Sense) lines)

–

Balancing lines (pins Sx and Bx_x-1)

•

Bottom layer: analog COM lines and Digital lines

–

Isolated COM line (pins ISOHx/ISOLx)

–

Digital lines (pins GPIOx)

–

Regulators (pins VREG, VCOM, VTREF, VANA)

6.1.2

Ground connections

In order to achieve the best performances in terms of accuracy and EMC, care must be taken while designing

ground connections.

L9963E features 4 ground pins used as internal reference:

•

AGND:

is the reference plane for the L9963E internal analog circuitry and must be kept as “clean” as

possible in order not to catch noise from the nearby switching components. It can be used as 2nd layer of the

PCB to shield voltage sense lines routed on the 1st layer.

•

DGND:

is the reference plane for the L9963E internal digital circuitry and it introduces noise on the PCB

due to the logic switching activity. It must be separated from AGND plane and can be routed over the 2nd

PCB layer.

•

CGND: is the reference line for the L9963E internal communication circuitry. It is connected to the output

buffer of SDO line and it acts as a reference for the ISOHx and ISOLx signals. It can be joined with DGND

plane at device pin level.

•

GNDREF: is the reference line for the L9963E internal ADCs. It carries low current and must be connected

to the negative terminal of the battery pack, over the 1st layer, shielded by AGND as it was a cell voltage

sense line. This will guarantee a clean and precise reference for all the internal ADCs.

L9963E performances are guaranteed if ground shift between AGND/DGND/CGND/GNDREF is kept below 100

mV. Hence, all the planes/lines mentioned above must be joined on the same node. This node is normally

represented by the PCB connector to the battery pack ground, corresponding to the negative terminal of the first

cell (PACK_GND

In case the Hotplug circuitry is mounted, the grounds collection node becomes the drain terminal of the MOSFET

MHOT (refer to Figure 27).

L9963E

Application information

DS13636 - Rev 12

page 128/184

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