L9963E datasheet(131/184 Pages) STMICROELECTRONICS

131 / 184 page

6.1.3

Cell balancing (Force) and cell sensing (Sense) lines

To increase cell voltage measurement accuracy during balancing, the voltage drop over the PCB lanes connected

to the cells has to be minimized. In order to do so, voltage sense lines connected to L9963E Cx pins and cell

balancing lines connected to Sx/Bx_x-1 pins must be split as close as possible to the PCB connector.

As recommended in PCB Stackup, cell sense lines must be routed over the top layer, shielded by AGND, while

balancing lines can be routed over the 3rd layer. Splitting must be done after the ESD caps and ferrite beads, in

order to guarantee protection from strikes and EMI robustness. Figure 29 shows a layout example.

Figure 29. Example of best practice for splitting cell force and sense lines

6.1.4

Regulator capacitors

L9963E features only linear regulators, in order not to introduce any switching noise on the PCB. Nevertheless,

regulator capacitors must be placed as close as possible to the corresponding device pin in order to avoid loops

generated by long traces and filter any ripple caused by current absorption peaks.

Mounting capacitors on the bottom side of the PCB, close to the L9963E footprint is a good option.

6.1.5

ESD clamps for communication interfaces

Routing of the PCB traces connected to the ESD clamp of the vertical interface is critical in order to ensure

maximum reduction of the spikes.

Even if the ISOHx and ISOLx pins are connected to the ECU global pins through a transformer, this component

does not guarantee total protection against very fast spikes due to ESD strikes and/or sudden external shorts

to battery/ground. In fact, the transformer parasitic capacitance between primary and secondary windings (in the

order of magnitude of pF) is still able to couple very fast voltage transients from one side to the other.

In order to clamp such spikes, ST recommends using the D_ESD component in the ISO Lines Circuit. To

achieve maximum clamping effectiveness, recommendations shown in Figure 30 and Figure 31 must be followed,

in order to reduce parasitic effects due to the inductances of the PCB lanes.

L9963E

Layout recommendations

DS13636 - Rev 12

page 131/184

L9963E Scheda tecnica(PDF) 131 Page - STMicroelectronics