STPM098C datasheet(57/110 Pages) STMICROELECTRONICS

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In case VOUTn_UV_FAULT_LIMIT = 0x000 the related voltage monitor function is disabled and no detection is

performed.

In case VOUTn_OV_FAULT_LIMIT = 0x000 the related voltage monitor function is disabled and no detection is

performed.

The absolute value of the maximum input voltage slew rate detectable by VOUT monitor is given by

VOUT_adc_lsb/VOUT_adc_latency.

Figure 46. Output voltage monitor timing diagram

VSENn-VRTNn

VOUTn _OV

(Internal signal)

VOUTn_UV

(Internal signal)

VOUTn_OV_TH

T_vout_mon_detect_dly

OPERATIVE

VOUTn_OV_HYS

VOUTn_UV_HYS

OPERATIVE

VOUTn_UV_TH

VOUT_adc_rise_fall_diff_sr

T_vout_mon_detect_dly

Table 48. VOUT monitor electrical characteristics

Symbol

Parameter

Test condition

Min

Typ

Max Unit

Notes

VOUT_MON_th_lsb

VOUT monitoring threshold

step

7.616

Application

information

VOUT_MON_th_range

VOUT monitoring threshold

range

3.5

Application

information

T_vout_mon_detect_dly

VOUT monitoring detection

delay

CLK_SSM_EN = 0

100

μs

Application

information

3.12.3

Output current telemetry

Current of each phase is directly measured across input pins ISENn and CFILT/VREF1 by means of a dedicated

11-bit ADC converter. The digitized voltage information is made available on PMBus™ register

MFR_READ_IOUTn [n = 1, 2, 3, 4, 5, 6, 7, 8] for the single phase current and on the paged register

READ_IOUTm<15:0> [m = 1, 2] for the sum current on each loop.

Output stage telemetry ADC and the related monitoring unit design are based on the following DrMOS current

sense output characteristics:

STPM098C

Functional description

DS14440 - Rev 1

page 57/110

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