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ISO7720DWVR Scheda tecnica(PDF) 34 Page - Texas Instruments |
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ISO7720DWVR Scheda tecnica(HTML) 34 Page - Texas Instruments |
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34 / 51 page ![]() www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] 2X .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25] .016-.050 [0.41-1.27] .041 [1.04] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) SOIC - 1.75 mm max height D0008B SMALL OUTLINE INTEGRATED CIRCUIT 4221445/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15], per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B 5 4 PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A TYPICAL DETAIL A SCALE 2.800 ISO7720, ISO7721 SLLSEP3G – NOVEMBER 2016 – REVISED MAY 2024 www.ti.com 34 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: ISO7720 ISO7721 |
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