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LM4040C20ILP Scheda tecnica(PDF) 29 Page - Texas Instruments |
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LM4040C20ILP Scheda tecnica(HTML) 29 Page - Texas Instruments |
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29 / 61 page ![]() • Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring. • Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible and only make perpendicular crossings when absolutely necessary. 8.4.2 Layout Example DBZ (TOP VIEW) 1 CATHODE 2 3 ANODE Rsup Vsup CL GND GND Figure 8-5. DBZ Layout example www.ti.com LM4040A, LM4040B, LM4040C, LM4040D SLOS456P – JANUARY 2005 – REVISED MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: LM4040A LM4040B LM4040C LM4040D |
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