STA680TR datasheet(21/48 Pages) STMICROELECTRONICS

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DS5877 Rev 13

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STA680

General description

The architecture of STA680 consists of a mixed hardware/software implementation.

Computation-intensive functional blocks are implemented using custom logic. Software

implementation is more efficient for functional blocks where flexibility is needed.

2.1

Receiver system overview

Such flexibility enables the STA680 to support both the HD 1.0 single-channel, and HD 1.5

double-channel applications, as shown in Figure 4.

Figure 5 shows the internal simplified block diagram of the STA680.

The STA680 receives the digital base-band signal from the digital tuner (e.g. TDA7786 or

TDA7707) and extracts the HD-encoded audio and data services as shown in Figure 5.

STA680 is compatible with conventional base-band radio reception tuners (e.g. TDA7786 or

TDA7707).

Figure 5. Functional block diagram for HD Radio demodulating and decoding

2.2

HD Radio processing

The STA680 HD Radio decoder performs the processing of the IBOC signal. The native

internal processing data rate is 744.1875 kS/s for FM and 46.51171875 kS/s for AM.

The input I2S base-band interface accepts several input sample rates thanks to the

availability of a reconfigurable sample rate converter.The supported rates are: 650 kS/s,

675 kS/s, 744.1875 kS/s and 912 kS/s.

The STA680 is responsible for the detection, acquisition and demodulation of the IBOC

signal. This processing is mainly performed inside the Vectra DSP core. The demodulated

signal is then passed to the Hi-Fi processor for decoding and handling of data services. The

digital 44.1 kHz decompressed audio is streamed out by means of the Digital Audio

Interface.

The STA680 requires a 4Mwords x16bits external SDRAM (with up to 32Mword x16bits

supported) for data storage in order to process the HD Radio stream

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