L99DZ320 datasheet(93/146 Pages) STMICROELECTRONICS

93 / 146 page

Bit

Name

Description

The FS bit indicates the device was forced into a safe state due to the following failure conditions:

SR8 (0x8):

•

WDFAIL

•

V1UV(when UV is more than 2 ms)

•

TSD2

•

FORCED_SLEEP_TSD2_V1SC

SR3 (0x03):

•

SGNDLOSS

All control registers are set to default

Control registers are blocked for WRITE access except the following bits:

CR18 (0x3F):

•

TRIG

•

CAN_ACT

CR17 (0x3E):

•

Timer settings (bits 8…21)

CR14 (0x3B):

•

HS15_x (bits 8…11)

•

HS0_x (bits 12…15)

CR5 (0x32) to CR10 (0x37)

•

PWM frequency and duty cycles

CR1 (0x26)

•

V2_0

•

V2_1

0 = failsafe inactive (default)

1 = failsafe active

FS is cleared upon exit from failsafe mode (refer to chapter Section 3.7: Fail-safe mode)

1. Individual failure flags may be masked in the CR1 (0x26).

2. Bit may be masked in the CR1 (0x26), that is the bit is not included in the global status bit (GSB).

3. The open-load status flags may be masked in the CR1 (0x26), that is the open-load flag is included in the FE flag but it does

not set the GSB. TW failure status flags may be masked in the CR1 (0x26), that is the TW flag is included in the GW flag,

but it does not set the GSB.

L99DZ320

SPI Registers

DS14235 - Rev 5

page 93/146

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