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SN65ALS176DR Scheda tecnica(PDF) 7 Page - Texas Instruments

Il numero della parte SN65ALS176DR
Spiegazioni elettronici  SNx5ALS176, SN75ALS176A, and SN75ALS176B Differential Bus Transceivers
PDF  26 Pages
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Produttore elettronici  TI2 [Texas Instruments]
Homepage  https://www.ti.com
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SN65ALS176DR Scheda tecnica(HTML) 7 Page - Texas Instruments

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5.8 Electrical Characteristics - Receiver
over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
VIT+
Positive-going input threshold voltage VO = 2.7 V,
IO = –0.4 mA
0.2
V
VIT–
Negative-going input threshold
voltage
VO = 0.5 V,
IO = 8 mA
–0.2(2)
V
Vhys
Hysteresis voltage (VIT+– VIT–)
60
mV
VIK
Enable-input clamp voltage
II = –18 mA
–1.5
V
VOH
High-level output voltage
VID = 200 mV,
See Figure 6-6
IOH = –400 mA,
2.7
V
VOL
Low-level output voltage
VID = –200 mV,
SeeFigure 6
IOL = 8 mA,
0.45
V
IOZ
High-impedance-state output current VO = 0.4 V to 2.4 V
±20
μA
VI
Line input current
Other input = 0 V(3)
VI = 12 V
1
mA
VI = –7 V
–0.8
IIH
High-level-enable input current
VIH = 2.7 V
20
μA
IIL
Low-level-enable input current
VIL = 0.4 V
–100
μA
rI
Input resistance
12
20
kΩ
IOS
Short-circuit output current
VID = 200 mV,
VO = 0
–15
–85
mA
ICC
Supply current
No load
Outputs enabled
23
30
mA
Outputs disabled
19
26
(1)
All typical values are at VCC = 5 V, TA = 25°C.
(2)
The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for
common-mode input voltage and threshold voltage levels only.
(3)
This applies for power on and power off. Refer to TIA/EIA-485-A for exact conditions.
5.9 Switching Characteristics - Receiver
SN65ALS176
over recommended ranges of supply voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
tpd
Propagation time
VID = –1.5 V to 1.5 V,
See Figure 6-7
CL = 15 pF,
25
ns
tsk(p)
Pulse skew(2)
VID = –1.5 V to 1.5 V,
See Figure 6-7
CL = 15 pF,
0
2
ns
tsk(lim)
Pulse skew(3)
RL = 54 Ω
See Figure 6-3
CL = 50 pF,
15
ns
tPZH
Output enable time to high level
CL = 15 pF,
See Figure 6-8
11
18
ns
tPZL
Output enable time to low level
CL = 15 pF,
See Figure 6-8
11
18
ns
tPHZ
Output disable time from high level
CL = 15 pF,
See Figure 6-8
50
ns
tPLZ
Output disable time from low level
CL = 15 pF,
See Figure 6-8
30
ns
(1)
All typical values are at VCC = 5 V, TA = 25°C.
(2)
Pulse skew is defined as the |tPLH– tPHL| of each channel of the same device.
(3)
Skew limit is the maximum difference in propagation delay times between any two channels of any two devices.
www.ti.com
SN65ALS176, SN75ALS176
SN75ALS176A, SN75ALS176B
SLLS040I – AUGUST 1987 – REVISED JANUARY 2023
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: SN65ALS176 SN75ALS176 SN75ALS176A SN75ALS176B



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