ICS4002AI01L datasheet(7/14 Pages) IDT

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ICS844002I-01

FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER

ICS844002AGI-01 REV. C SEPTEMBER 28, 2007

Parameter Measurement Information, continued

Differential Offset Voltage Setup

Application Information

Power Supply Filtering Technique

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. The ICS844002I-01 provides separate

power supplies to isolate any high switching noise from the outputs

to the internal PLL. VDD, VDDA and VDDO should be individually

connected to the power supply plane through vias, and bypass

capacitors should be used for each pin. To achieve optimum jitter

performance, power supply isolation is required. Figure 1

illustrates how a 10

Ω resistor along with a 10µF and a 0.01µF

bypass capacitor should be connected to each VDDA pin.

Figure 1. Power Supply Filtering

Recommendations for Unused Input and Output Pins

Inputs:

LVCMOS Control Pins

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1k

Ω resistor can be used.

REF_CLK INPUT

For applications not requiring the use of the reference clock,

it can be left floating. Though not required, but for additional

protection, a 1k

Ω resistor can be tied from the REF_CLK to

ground.

Crystal Inputs

For applications not requiring the use of the crystal oscillator input,

both XTAL_IN and XTAL_OUT can be left floating. Though not

required, but for additional protection, a 1k

Ω resistor can be tied

from XTAL_IN to ground.

Outputs:

LVDS Outputs

All unused LVDS output pairs can be either left floating or

terminated with 100

Ω across. If they are left floating, we

recommend that there is no trace attached.

➤

100

out

LVDS

DC Input

VOD/∆ VOD

VDD

VDDA

2.5V

Ω

10µF

.01µF

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