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TLV2170IDR Scheda tecnica(PDF) 24 Page - Texas Instruments |
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TLV2170IDR Scheda tecnica(HTML) 24 Page - Texas Instruments |
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24 / 47 page ![]() NC ±IN +IN V± V+ OUTPUT NC NC VS+ VS± GND Ground (GND) plane on another layer VOUT VIN GND Run the input traces as far away from the supply lines as possible RF RG Place components close to device and to each other to reduce parasitic errors Use low-ESR, ceramic bypass capacitor GND Use a low-ESR, ceramic bypass capacitor VIN VOUT RG RF + ± 24 TLV170, TLV2170, TLV4170 SBOS782A – NOVEMBER 2016 – REVISED MAY 2018 www.ti.com Product Folder Links: TLV170 TLV2170 TLV4170 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated 10.2 Layout Example Figure 33. Schematic Representation Figure 34. Op Amp Board Layout for a Noninverting Configuration |
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