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TMP112 Scheda tecnica(PDF) 35 Page - Texas Instruments |
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TMP112 Scheda tecnica(HTML) 35 Page - Texas Instruments |
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35 / 46 page ![]() Not to scale 0.01µF 5k 5k I 2C Bus Via to Power Plane Via to Internal Plane Internal Layer Trace Top/Bottom Layer Trace Via to Ground Plane 3 4 2 5 1 Center Pin Layout (Address Variant) 2 1 3 5 4 Figure 8-7. DPW Layout Example When using the ALERT pin of the DRL package, the layout is shown as Figure 8-8: www.ti.com TMP112-Q1, TMP112D-Q1 SLOS887G – SEPTEMBER 2014 – REVISED MAY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TMP112-Q1 TMP112D-Q1 |
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