Data Sheet

ADRF5448

THEORY OF OPERATION

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Rev. 0 | 12 of 14

The ADRF5448 integrates a driver to perform the logic function

internally and to provide the advantage of a simplified control

interface. The driver features four digital control input pads (V1, V2,

EN, and LS) that control the state of the RF paths, determining

which RF port is in the insertion loss state and which RF port is in

the isolation state, see Table 6.

The LS pad allows the user to define the control input logic se-

quence for the RF path selections. The logic level applied to the V1

and V2 pads determines which RF port is in the insertion loss state

while the other three paths are in the isolation state.

When the EN pad is logic high, all four RF paths are in an isolation

state regardless of the logic state of LS, V1, and V2. The RF

ports are terminated to internal 50 Ω resistors, and RFC becomes

reflective.

RF INPUT AND OUTPUT

All of the RF ports (RFC, RF1 to RF4) are DC-coupled to 0 V,

and no DC blocking is required at the RF ports when the RF line

potential is equal to 0 V.

The RF ports are internally matched to 50 Ω. Therefore, external

matching networks are not required.

The insertion loss path conducts the RF signal between the RF

common port and the selected RF throw port. The switch design is

bidirectional with equal power handling capabilities. The RF input

signal can be applied to the RF common port or the selected

RF throw port. The isolation paths provide high loss between the

insertion loss path and the unselected RF throw ports that are

terminated to internal 50 Ω resistors.

POWER SUPPLY

The ADRF5448 requires a positive supply voltage applied to the

VDD pad and a negative supply voltage applied to the VSS pad.

Bypassing capacitors are recommended on the supply lines to filter

high frequency noise.

The power-up sequence is as follows:

1. Connect to GND.

2. Power up VDD and VSS. Power up VSS after VDD to avoid

current transients on VDD during ramp up.

3. Power up the digital control inputs. The order of the digital

control inputs is not important. However, powering the digital

control inputs before the VDD voltage supply can inadvertently

forward bias and damage the internal ESD structures. To avoid

this damage, use a series 1 kΩ resistor to limit the current

flowing into the control pad. Use pull-up or pull-down resistors

if the controller output is in a high impedance state after VDD is

powered up, and the control pads are not driven to a valid logic

state.

4. Apply the RF signal.

The power-down sequence is the reverse order of the power-up

sequence.

Table 6. Control Voltage Truth Table

Digital Control Inputs

RFx Paths

EN

LS

V1

V2

RF1 to RFC

RF2 to RFC

RF3 to RFC

RF4 to RFC

Low

Low

Low

Low

Insertion loss (on)

Isolation (off)

Isolation (off)

Isolation (off)

Low

Low

High

Low

Isolation (off)

Insertion loss (on)

Isolation (off)

Isolation (off)

Low

Low

Low

High

Isolation (off)

Isolation (off)

Insertion loss (on)

Isolation (off)

Low

Low

High

High

Isolation (off)

Isolation (off)

Isolation (off)

Insertion loss (on)

Low

High

Low

Low

Isolation (off)

Isolation (off)

Isolation (off)

Insertion loss (on)

Low

High

High

Low

Isolation (off)

Isolation (off)

Insertion loss (on)

Isolation (off)

Low

High

Low

High

Isolation (off)

Insertion loss (on)

Isolation (off)

Isolation (off)

Low

High

High

High

Insertion loss (on)

Isolation (off)

Isolation (off)

Isolation (off)

High

Low or high Low or high Low or high Isolation (off)

Isolation (off)

Isolation (off)

Isolation (off)