Data Sheet

ADRF5703

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 8 of 19

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

D6/CLK

Parallel Control Input for 16dB Attenuator Bit. Serial Clock Input (CLK). See the Theory of Operation section for more information.

See Figure 7 for the interface schematic.

2

LE

Latch Enable Input. See the Theory of Operation section for more information. See Figure 7 for the interface schematic.

3

PS

Parallel or Serial Control Interface Selection Input. See the Theory of Operation section for more information. See Figure 7 for the

interface schematic.

4, 6 to 13, 15, 16

GND

Ground. The GND pins must be connected to the RF and DC ground of the PCB.

5

ATTIN

Attenuator Input. No DC blocking capacitor is necessary when the RF line potential is equal to 0V DC. See Figure 4 for the interface

schematic.

14

ATTOUT

Attenuator Output. No DC blocking capacitor is necessary when the RF line potential is equal to 0V DC. See Figure 4 for the

interface schematic.

17

VSS

Negative Supply Input. See Figure 9 for the interface schematic.

18

VDD

Positive Supply Input. See Figure 8 for the interface schematic.

19

D0

Parallel Control Input for 0.25dB Attenuator Bit. See the Theory of Operation section for more information. See Figure 5 for the

interface schematic.

20

D1

Parallel Control Input for 0.5dB Attenuator Bit. See the Theory of Operation section for more information. See Figure 5 for the

interface schematic.

21

D2

Parallel Control Input for 1.0dB Attenuator Bit. See the Theory of Operation section for more information. See Figure 5 for the

interface schematic.

22

D3

Parallel Control Input for 2dB Attenuator Bit. See the Theory of Operation section for more information. See Figure 5 for the interface

schematic.

23

D4/SEROUT

Parallel Control Input for 4dB Attenuator Bit. Serial Data Output (SEROUT). See the Theory of Operation section for more

information. See Figure 6 for the interface schematic.

24

D5/SERIN

Parallel Control Input for 8dB Attenuator Bit. Serial Data Input (SERIN). See the Theory of Operation section for more information.

See Figure 7 for the interface schematic.