HCF4527B datasheet(7/13 Pages) STMICROELECTRONICS

7 / 13 page

DYNAMIC ELECTRICAL CHARACTERISTICS (continued)

Symbol

Parameter

Test Conditions

Value

Unit

VDD (V)

Min.

Typ.

Max.

Inhibit Input Removal Time

240

120

130

110

Set Remova Time

150

Clear Removal Time

APPLICATION NOTE

For fractional multipliers with more than one digit,

HCC/HCF4527B devices may be cascated in two

different modes: the Add mode and the Mltiply mode

(see figures 1 and 2).

When two units are cascated in Add mode and pro-

grammed to 9 and 4 respectively, the more signifi-

cant unit will have 9 output pulses for every 10 input

pulses and the other unit will have 4 output pulses

for every 100 input pulses for a total of:

100

In the multiply mode, the fraction programmed into

the first rate multiplier is multiplied by the fraction

programmed into the second one:

If N1 = 9 and N2 =4

fout2 =

fout1

fclock

fout2

× 



fclock







100

fclock

Therefore 36 output pulses for every 100 clock input

pulses.

HCC/HCF4527B

7/13

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