Synchronous rectification.

Very high efficiency is achieved at high load current with the synchronous rectification technique, which

is particularly advantageous because of the low output voltage. The low-side MOSFET, that is the syn-

chronous rectifier, is selected with a very low on-resistance, so that the paralleled Schottky diode is not

turned on, except for the small time in which neither MOSFET is conducting. The effect is a considerable

reduction of power loss during the recirculation period.

Although the Schottky might appear to be redundant, it is not in a system where a very high efficiency is

required. In fact, its lower threshold prevents the lossy body-diode of the synchronous rectifier MOSFET

from turning on during the above mentioned dead-time. Both conduction and reverse recovery losses are

cut down and efficiency can improve of 1-2% in some cases. Besides a small diode is sufficient since it

conducts for a very short time.

As for the 3.3V section only, the synchronous rectifier is also involved in the 12 V linear regulator opera-

tion (see the relevant section). See also the "Power Management" to see how both synchronous rectifi-

ers are used to ensure zero voltage output in stand-by conditions or in case of overvoltage.

Pulse-skipping operation.

To achieve high efficiency at light load current as well, under this condition the regulators change their

operation (unless this feature is disabled): they abandon PWM and enter the so-called pulse-skipping

mode, in which a single switching cycle takes place every many oscillator periods.

not exceed 26mV while the high-side MOSFET is conducting. When the reset signal of the output latch

voltage above its nominal value for a while. The oscillator pulses now set the output latch only when the

feedback signal indicates that the output voltage has fallen below its nominal value. In this way, most of

oscillator pulses is skipped and the resulting switching frequency is much lower, as expressed by the fol-

lowing relationship:

= K

⋅

2

L



1

−







where K = 3.2

the losses due to switching and to gate-drive,

which mostly account for power dissipation at low

output power, are considerably reduced.

The +5.1V section can work with the input voltage

very close to the output one, where the current

waveform may be so flat to prevent pulse-skipping

from being activated. To avoid this, the pulse-skip-

ping threshold (of the +5.1V section only) is

roughly halved at low input voltages, as shown in

fig. 3. Under this condition, in the above formula

the constant K becomes 12.8

When in pulse-skipping, the output voltage is

some ten mV higher than in PWM mode, just be-

cause of its mode of operation. If this "load regula-

tion" effect is undesirable for any reason, the pulse

skipping feature can be disabled (see "Power

Management" section) to the detriment of effi-

ciency at light load.

MOSFET’s drivers

To get the gate-drive voltage for the high-side N-channel MOSFET a bootstrap technique is employed. A

capacitor is alternately charged through a diode from the 5V REG5 line when the high-side MOSFET is

OFF and then connected to its gate-source leads by the internal floating driver to turn the MOSFET on.

The REG5 line is used to drive the synchronous rectifier as well, and therefore the use of low-threshold

Vth

Vin

26 mV

13 mV

5.5V 5.8V

6.3V

20V

Figure 3: Pulse-skipping threshold vs. input

voltage (+5.1V section only).

DETAILED FUNCTIONAL DESCRIPTION (continued)

L4992

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